1. Field of the Invention
The present invention relates to a pictorial or video data recording method for a high definition video cassette tape recorder (hereinafter "HDVCR") or a digital video cassette tape recorder (hereinafter "DVCR"), and in particular to an improved video data recording method for a HDVCR or DVCR capable of very densely recording compressed video data on a video tape by improving a formatting method.
2. Description of the Conventional Art
Referring to FIG. 1, the conventional video data recording method for a high definition digital video cassette tape recorder includes a discrete cosine transforming circuit 1 provided for discrete-cosine-transforming an input video data (IVD) inputted thereto, a quantization circuit 2 provided for quantizing the output data outputted from the discrete cosine transforming circuit 1, a variable length coding circuit 3 provided for variable-length-coding the output data outputted from the quantization circuit 2 in a form of a bit stream, a formatting circuit 4 provided for formatting the output data outputted from the variable length coding circuit 3 into the type of data which can be recorded on a tape T, an error correction coding circuit 5 provided for adding an error correction code to the output data outputted from the formatting circuit 4, a record amplifying circuit 6 provided for amplifying the output data outputted from the error correction coding circuit 5 and for recording the amplified data on the tape T through a head H1, a reproduction amplifying circuit 7 provided for amplifying the recorded data of the tape T reproduced by a head H2, an error correction decoding circuit 8 provided for decoding the error correction code added to the output data outputted from the reproduction amplifying circuit 7 and for correcting the decoded video data, a deformatting circuit 9 provided for receiving the output data outputted from the error correction decoding circuit 8 and for formatting the received data into the original data form, a variable length decoding circuit 10 provided for variable-length-decoding the output data outputted from the deformatting circuit 9, a reverse quantization circuit 11 provided for reverse-quantizing the output data outputted from the variable length decoding circuit 10, and a reverse discrete cosine transforming circuit 12 provided for reverse-discrete-cosine-transforming the output data outputted from the reverse quantization circuit 11 and for outputting the original video data (OVD).
The operation of the conventional high definition VCR will now be explained with reference to FIGS. 2A through 4.
To begin with, as a reproducing mode is set, when a video data IVD of a frame is inputted into the discrete cosine transforming circuit 1 as shown in FIG. 1, the discrete cosine transforming circuit 1 transforms the video data IVD into a macro block consisting of four luminescent component DCT blocks (Y) shown in FIG. 2A and two chrominance component DCT block (Cr and Cb) through a shuffling process. Here, a segment block consists of five macro blocks, i.e., thirty DCT blocks. As shown in FIG. 2B, each luminescent component DCT block has 14 bytes, and each chrominance component DCT block has 10 bytes.
In addition, the video data consisting of one unit block by the discrete cosine transforming (DCT) circuit 1 is compressed by the quantization circuit 2 and inputted into the variable length coding circuit 3.
Thereafter, the variable length coding circuit 3 scans each DCT block in a manner of zig-zag and outputs the video data in a form of bit streams after a variable length coding, and the formatting circuit 4 performs a formatting step so as to record the serially outputted bit streams on the tape T.
Here, as shown in FIG. 4, the above described formatting step will now be explained in more detail, which consists of three steps.
In the first process, the bit streams are outputted from the variable length coding circuit 3, and the bit streams as shown in FIG. 3A-1 are compressively stored in a macro block of "j=0." That is, the bit stream of "A1+A1" is compressively stored in a DCT block of a location (0,0) which is "j=0, i=0." The bit stream of "B1" is compressively stored in a DCT block of a location of (0,1). The bit stream of "C1" is compressively stored in a location (0,2). The bit stream of "D1+D1" is compressively stored in a location of (0,3). The bit stream of "E1" is compressively stored in a location of (0,4). The bit stream of "F1" is compressively stored in a location of (0,5).
The bit streams each compressively stored in one of six DCT blocks which are in the macro block of "j=0" as shown in FIG. 3B-1, are stored in the DCT block of six compressed regions which are formed in the video unit of "j'=0"--step 2 in FIG. 4. That is, the bit stream A1 compressively stored in a DCT block provided in a location of (0,0) is stored in a DCT block of a compression region provided in a location of "j'=0, i'=0" (0,0), the bit stream B1 compressively stored in a location of (0,1) is compressively stored in a DCT block provided in a location of (0,1) and the bit stream C1 compressively stored in a DCT block of (0,2) is compressively stored in a DCT block of a compression region provided in a location of (0,2).
In addition, the bit stream D1 compressively stored in a DCT block of (0,3) is compressively stored in a DCT block of a compression region of (0,3), the bit stream E1 compressively stored in a DCT block of (0,4) is compressively stored in a DCT block of a compression region of (0,4), and the bit stream F1 compressively stored in a DCT block of (0,5) is compressively stored in a DCT block of a compression region (0,5).
In addition, as shown in FIG. 3B-1, the DCT block consisting of six compression regions can include full regions and empty regions.
Here, as shown in FIG. 3B-1, the remaining bit streams A1' and D1' obtained after the video segment provided in locations (0,0) and (0,3) is filled therewith, are serially stored in a memory MR(0) as shown in FIG. 3C-1 (step 3 in FIG. 4).
Similarly, the bit streams as shown in FIGS. 3A-2 to 3A-5 are compressively stored in the six DCT blocks provided in macro blocks of "j=1", "j=2", "j=3", and "j=4", respectively, as shown in FIGS. 3B-2 to 3B-5. Each of these bit streams is stored respectively in DCT blocks of six compression regions provided in a video unit of "j'=1", "j'=2", "j'=3" or "j'=4" (ST2), and the remaining bit streams obtained after the DCT blocks are filled therewith are correspondingly stored in the memories MR(1)-MR(4) as shown in FIGS. 3C-2 to 3C-5 (Step 3 in FIG. 4).
Here, as shown in FIGS. 3B-1 to 3B-5, at each end of the bit stream stored in each DCT block, a mark of EOB--End of Block--is provided.
In the second process (steps 4 and 5) the remaining bit stream compressively stored in each of the memories MR(0) through MR(4) is compressively stored in the empty space of a video unit of "j=0"--Step 4, after the remaining bit stream is stored in each of memories MR(0) through MR(4) in the step 3. In addition, the bit stream stored in the remaining memories MR(1) through MR(4) is compressively stored in the empty space of each video unit region.
That is, as shown in FIGS. 3D-1 to 3D-5, the bit stream compressively stored in the memory MR(0) is stored in the empty space of the video unit region of "j=0" in an order from "i'=0" to "i'=5"--Step 4, the bit stream stored in the memory MR(1) is compressively stored in the video unit region of "j'=1" in an order from "i'=0" to "i'=5"--Step 4, and the bit stream stored in the remaining memories MR(2) through MR(4) is compressively stored in each video unit region in the same manner as described above Step 4.
In addition, as shown in FIGS. 3D-1 to 3D-5, the remaining bit streams D1", B2", A3', D3', F3', B4" and D4" obtained after the bit streams stored in the memories MR(0) through MR(4) are stored in the empty spaces of the video units of "j'=0 to "j'=4", are stored in a memory VR as shown in FIGS. 3E-1 to 3E-5--Step 5.
In the third process (steps 6-9) as shown in FIG. 3F, the bit stream stored in the memory VR in the step 5 is serially stored in the empty portions of video unit regions of "j'=0" in the order from "i'=0" to "i'=5", "j'=1" in the order from "i'=0" to "i'=5," etc.--Step 6. If the bit stream D1" in the memory VR is smaller than the size of the empty space of the first DCT block having a space, the bit stream D1" is stored therein and the next empty space in the DCT blocks are searched to store the next bit stream in the memory VR.
The size of the empty space of the last DCT block having a space is compared to the size of the bit stream in the memory VR--Step 7.
As a result of the comparison, if the size of the empty space of such DCT block is larger than the size of the bit stream in the memory VR, this bit stream is stored in the video segment region thereof (i.e., in the empty space of the DCT block)--Step 8. However, if the size of the empty space of the DCT block is smaller than the size of the bit stream in the memory VR, the compared bit stream and all of the remaining bit streams stored in the memory VR are cleared, and the remaining region of the video segment remains empty--Step 9.
The above described formatting process of the video data outputted from the variable length coding circuit 3 is performed by the formatting circuit 4 so as to form data which can be recorded on the tape T. This formatted pictorial data is outputted to the error correction coding circuit 5, in which the error correction code is added. The video data with the error correction code is amplified by the record amplifying circuit 6 and is recorded on the tape T through the head H1.
Meanwhile, when the data recorded on the tape T is reproduced by the reproduction amplifying circuit 7 in accordance with a reproduction mode, the error correction decoding circuit 8 decodes the error correction codes added to the reproduction data and corrects the errors of the reproduced pictorial data, and then the deformatting circuit 9 receives the error-corrected data and transforms the recording format state into the original state.
At this time, the variable length decoding circuit 10 receiving the output data outputted from the deformatting circuit 9 recovers the video data in accordance with the variable length code, and the reverse quantization circuit 11 performs a reverse quantization on the recovered data, so that the compressed video data is decompressed.
Thereafter, the reverse discrete cosine transforming circuit 12 receiving the output data outputted from the reverse quantization circuit 11 performs a reverse discrete cosine transforming on the data inputted thereto and outputs the original video data.
However, in the conventional video data recording method, since the formatting process ends when the size of the last empty space of the partially filled video segment is smaller than the size of the video data stored in a memory, the empty space of the partially filled video segment remains empty and the recording space of a tape can not be effectively used. Further, bit stream data is lost because all the remaining bit streams stored in a memory VR are discarded when the size of the last empty space of the partially filled video segment is smaller than the size of the remaining bit stream. In addition, the picture quality during reproducing is poor.